Libero Design Software
Libero® SoC Design Suite offers high productivity with its comprehensive, easy-to-learn, easy-to-adopt development tools for designing with Microsemi FPGAs and SoC FPGAs that supports Microsemi's IGLOO2, SmartFusion2, RTG4, SmartFusion, IGLOO , ProASIC3 and Fusion families. The suite integrates industry standard Synopsys Synplify Pro® synthesis and Mentor Graphics ModelSim® Simulation with best-in-class constraints management, debugcapabilities and secure production programming support.
Comprehensive
- Design entry: Multiple approaches using SmartDesign, HDL, or embedded design flows
- Simulation: Functional, gate-level, and timing verification using Mentor Graphics ModelSim ME
- Synthesis: Design optimization for power and performance using Synopsys Synplify Pro ME and Synphony Model Compiler ME
- Place and Route: Advanced, incremental, power-driven, and multi-pass layout options
- Power analysis: In-depth visualization of power consumption for each individual design element using SmartPower
- Timing analysis: Support for multiple constraint scenarios to optimize timing using SmartTime
- Programming: Complete solution with industry's first Secure Production Programming Solution (SPPS)
- Debug: Best-in-class debug solution with SmartDebug and Synopsys Identify ME